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authorAijun Shi2020-06-16 04:50:21 +0000
committerJonah Graham2020-06-16 13:39:43 +0000
commit30845347d0420369ca3c361fde0b61c3911c969b (patch)
treed831bb457c016d21fe1b8503c9b0b143cba76ead
parent8b039257b7066dd89155397ea4de83676d2461a9 (diff)
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Bug 564232 - Add cpu risc for RISC-V need to support.
Change-Id: Ib62ed14f3c0dbe4375da41dba7209b27e034c53e Signed-off-by: Aijun Shi <Aijun.Shi@windriver.com>
-rw-r--r--core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java6
1 files changed, 6 insertions, 0 deletions
diff --git a/core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java b/core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java
index b9a93317864..ba8d81773f9 100644
--- a/core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java
+++ b/core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java
@@ -158,6 +158,9 @@ public class Elf {
/** @since 6.0 */
public static final int EM_AARCH64 = 183;
+ /** @since 7.0 */
+ public static final int EM_RISCV = 243;
+
public static final int EM_NIOS = 0xFEBB;
public static final int EM_CYGNUS_POWERPC = 0x9025;
public static final int EM_CYGNUS_M32R = 0x9041;
@@ -908,6 +911,9 @@ public class Elf {
case Elf.ELFhdr.EM_RS08:
attrib.cpu = "rs08"; //$NON-NLS-1$
break;
+ case Elf.ELFhdr.EM_RISCV:
+ attrib.cpu = "riscv"; //$NON-NLS-1$
+ break;
case Elf.ELFhdr.EM_NONE:
default:
attrib.cpu = "none"; //$NON-NLS-1$

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